The present invention relates to the field of memory devices, and, more particularly, to a method of re-programming an array of non-volatile memory cells after an erase operation.
As is known, a non-volatile memory retains information stored therein when no power is supplied to it. It is usually set up as an array of memory cells including a plurality of rows and columns.
In particular, in NOR architecture Flash type non-volatile memories, individual memory cells may be selectively programmed (i.e., brought to a logic level 0), and the array may be erased (i.e., brought to a logic level 1). Either the whole array or subarrays (or sectors), which typically have a size of 512 k cells, may be erased.
To store logic information in a non-volatile manner, the state of an elementary memory cell is changed by having the electric charge contained in a floating gate electrode altered by special physical mechanisms. On the other hand, to read stored information, i.e., recognize the state of the memory cell, a value of a current Icell flowing through the column that includes the cell to be read is measured.
In particular, as shown schematically in FIG. 1, when the current Icell is smaller than a suitable reference Read (known as the read reference), the cell is recognized to be in the logic 0 state, or the logic 1 state in the opposite case. In the case of a Flash memory device, an erase operation requires that all the cells in at least one sector be brought to the logic 1 state. A Flash memory device user executes the operation by simply entering a specific command.
Nonetheless, as technology has progressed, the operation of erasing a Flash memory device has grown to become more and more sophisticated and complex. However, this development of the erase operation is not visible to the user, because the increased sophistication and complexity is handled inside the Flash memory devices by on-board xe2x80x9cintelligencexe2x80x9d provided in continually expanding quantities. In other words, it can be said that the erase operation has been made ever simpler, as seen from the user""s point of view, since the first generation of Flash memories, although the underlying operations have become more complex.
To execute the erase operation, a series of voltage pulses are applied to the memory cells inside the Flash memory device so that electrons may be extracted from the floating gate by the tunnel effect. In general, each voltage pulse is followed by a verification operation to verify the memory cells"" status to determine if the cells are in the desired logic 1 state.
As noted above, the logic 1 state corresponds to a cell reading current Icell that is larger than the reference value Read, or it may correspond to a cell threshold value Vread that is below a given value Vev, known as the erase verify level. Similarly, a threshold value Vpv, known as the program verify level, is used for a cell verifying operation after a program operation. The erase pulses are repeatedly applied to a cell until the condition for the threshold voltage of a cell is met, i.e., until:
Vth less than Vev.xe2x80x83xe2x80x83(1) 
With Flash memory devices, the erase operation is carried out within at least one sector until the cell with the highest threshold in the array or the sector (known as the xe2x80x9cslowxe2x80x9d cell) is recognized to be at logic 1. It should be noted that, since the erase operation is a non-selective one, even cells that have already been identified as being at logic 1 would be erased, thus attaining lower, and occasionally much lower (a few Volts), threshold values than the erase verify level Vev, as shown schematically in FIGS. 2 and 3.
However, to correctly read the information stored in a NOR architecture array of memory cells, it is necessary that, as a voltage of 0 Volt is applied to the array rows, all the cells in the memory array are turned xe2x80x9coffxe2x80x9d, i.e., that the drain current of all the cells is smaller than the read current by at least 4-5 orders of magnitude. It should be noted that a voltage of 0 Volts corresponds to the voltage value of the unselected rows of cells during normal operation of the memory device, as well as to the voltage value of the unselected rows with the memory device in the read mode.
From the standpoint of the threshold voltage Vth of the memory cells, a reading operation is correct when no cell in the array has a lower threshold than a suitable value Vdv, known as the depletion verify level. Thus, the spread of the cell threshold voltage Vth in a Flash memory device, following an erase operation, should not be an arbitrary one but instead meet the following requirements if the NOR architecture memory array is to perform correctly in the read mode. These requirements are that it should be less than the erase verify value Vev to ensure the logic 1 state, and it should be more than the depletion verify voltage value Vdv to ensure correct reading.
In other words, the threshold voltage Vth of the erased cells should be within the following range:
Vdv less than Vth less than Vev,xe2x80x83xe2x80x83(2) 
as schematically shown in FIG. 4.
To summarize, to avoid possible malfunctioning in the read mode of the Flash memory device, upon completion of an erase operation, the highest threshold cell should be correctly identified as being at logic 1. Further, the lowest threshold cells should produce substantially no parasitic currents in the columns of the NOR array.
In first-generation Flash memories, these conditions were usually met by a suitably set erase verify value Vev, and by the erase operation being limited to just the step of applying voltage pulses and verifying the logic 1 state of the cells. In later generations, the erase verify point (i.e., the erase verify value Vev) was gradually set at lower values by reason of the shift. That is, it was first set toward single supply and then toward low and very low voltage applications, and more recently, to provide multi-level memories.
In addition, the threshold spread of the memory cells upon completion of an erase operation may undergo variations from factors such as process handling, the erase mode selected, occasional errors in the conduction characteristics of tunnel dielectrics, and device aging in terms of program/erase cycles (hereinafter, P/E cycles). As such, in view of these and other considerations of current memories, and even more so in view of future generations of non-volatile memories, a memory cell array may not be in a condition to perform reliably at the end of an erase operation.
When the threshold spread of the cells exceeds the limits set by the range (2) above (FIG. 3), a common practice has been to consolidate the erase operation with a subsequent re-program operation. That is, those cells which have a threshold that is too low are brought up to a value above the depletion verify value Vdv, while still below the erase verify value Vev, as shown schematically in FIGS. 4 and 5.
This re-program operation following an erase operation should be a xe2x80x9cslightxe2x80x9d one, which is generally known as soft programming. This operation is set apart from the true program operation that brings the cell to the logic 0 state and is carried out upon a specific command from a memory user in that the soft programming operation is performed automatically by the memory device at the end of a true erase operation. It is, therefore, not visible to the user. As previously stated, during a soft program operation, all those memory cells which have their threshold below the depletion verify level Vdv are programmed until they overcome this reference value.
Current re-programming procedures or algorithms provide for a series of program pulses at increasing gate voltage to be applied to the individual cells in a sector. The starting voltage should be suitably low to satisfy two conditions, namely that the charge pumps in the generating circuit of the re-programming voltage should not be overloaded, and the cells should not be programmed beyond the erase verify value Vev.
Before those cells which have their threshold below the depletion verify value are selectively re-programmed, a number of low-voltage gate pulses are sometimes applied to all the cells in a sector. In other cases, depending on the re-programming algorithm being used, it is necessary, or at least safer in terms of reliability, to apply the re-programming pulses to all the cells in one column.
Therefore, the design of a Flash memory preferably allows re-programming of the memory cells under widely varying operational conditions that are dependent on the pattern of the threshold spread after an erase operation, as well as on the parasitic currents produced in the cell columns from applying erase pulses, on the operating temperature, on the age of the memory device, and on the alteration of the conduction characteristics induced by the tunnel effect in the oxides. Furthermore, with respect to the performance of the memory device in terms of time needed to execute the erase operation, an ideal target would be to remove all need to have any cells re-programmed, and hence, any depletion verify value Vdv to be set. Yet, in reality, this is not possible for the reasons set forth above.
Thus, an ideal setting of the depletion verify value Vdv is the lowest value consistent with the need to have the device perform as designed. In actual practice, however, the depletion verify value Vdv that is an ideal value for a new device (i.e. one having zero P/E cycles) will no longer be ideal for the same device once aged (i.e., after thousands or tens of thousands of P/E cycles), or if operated at a different temperature.
Consequently, to provide memory devices of lasting reliability, the depletion verify value Vdv is typically set at the highest of all the xe2x80x9cidealxe2x80x9d values under the different operational conditions of the memory device. For example, a depletion verify value Vdv can be used with a Flash memory in a hard-disk application which will correspond to that required for the memory to perform correctly after 100,000 P/E cycles at a running temperature of 120xc2x0 C.
In other words, since the appropriate depletion verify value Vdv varies with the memory device conditions, it is factory set such that it will ensure proper performance of the device under the most severe of its expected conditions of use. However, this single initial setting is likely to later complicate the re-program operation from the first cycles of the memory device. In addition, many such devices may never have to face conditions that warrant a depletion verify value Vdv selected for worst case.
The underlying technical problem of this invention is to provide a method of re-programming a non-volatile memory, such as a NOR architecture flash memory, after an erase operation, and a related memory device which overcome the limitations and shortcomings of the prior art noted above.
Generally speaking, the present invention provides a method of re-programming a memory after an erase operation, based on dynamically, or adaptively, handling the setting of the depletion verify value. As such, the above-noted technical problem is addressed in accordance with the present invention by a method of re-programming an array of non-volatile memory cells subsequent to an erase operation where a re-program operation is executed after the erase operation to restore a threshold voltage of the memory cells to a higher value than a depletion verify value.
More particularly, the method may include identifying a first value of the depletion verify voltage, executing the re-program operation using the value of the depletion verify voltage (Vdv), and verifying the array of re-programmed cells for reliability in the read mode. Further, if the outcome of the verifying step is favorable, program operation may be ended. Otherwise, the value of the depletion verify voltage may be modified, and the re-program operation again executed using the modified value of the depletion verify voltage, as automatically adjusted based upon the operating conditions of the memory array.
A non-volatile memory device in accordance with the invention includes an array of non-volatile memory cells divided into rows and columns. At least one column parasitic current control circuit is connected to a circuit for generating values of a depletion verify voltage and changing the values to suit the conditions of the memory device.